Photolithography tools are used to print small features on semiconductor (e.g., silicon) wafers in the fabrication of integrated circuits (ICs). Photolithography tools are also used for back-end processes that involve, for example, forming patterns to define layer interconnects. Layer interconnects provide electrical power to drive the IC. The photolithography tools are also used in the back-end process to pattern metal pathways of the high-speed communication bus used to transmit control logic and data input/output (I/O) of the IC.
In the past two decades or so, the size of the silicon wafers used in manufacturing has grown from (200 mm) 8″ to (300 mm) 12″, with (450 mm) 16″ now being considered. The IC manufacturing cost is related to two key factors: yield and throughput (i.e., wafers/hour). When the yield approaches 100%, the IC costs are largely defined by the throughput of the manufacturing process.
One way to increase throughput is to increase the die size on the wafer. Another way is to increase the number of die that can be imaged at one time. To do both, the photolithography tool needs to support multiple-die formats for large die so that the stepping (or scanning) time per wafer is reduced. This is more easily achieved in the coarser back-end layers that can be processed by unit-magnification (1×) photolithography tools.
What is needed is a robust but simple 1× projection optical system for a photolithography tool that operates at the i-line LED wavelength(s) and that has a field size capable of handling four to six die, and that also has a variable magnification that can at least partially compensate for registration errors that can occur in lithographic pattern overlay.